Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters

The steeply growing performance demands for highly power- and energy-constrained processing systems such as end-nodes of the Internet-of-Things (IoT) have led to parallel near-threshold computing (NTC), joining energy-efficiency benefits low-voltage operation with typical systems. Shared-L1-memory multiprocessor clusters are a promising architecture, delivering in order GOPS over 100 GOPS/W energy-efficiency. However, this level computational efficiency can only be reached by maximizing effective utilization elements (PEs) available clusters. Along effort, optimization PE-to-PE synchronization communication is critical factor performance. In article, we describe light-weight hardware-accelerated unit (SCU) tightly-coupled processors. We detail which enables fine-grain per-PE power management, its integration into an eight-core cluster RISC-V To validate effectiveness proposed solution, implemented advanced 22 nm FDX technology evaluated tunable microbenchmarks set real-life applications kernels. solution allows synchronization-free regions small 42 cycles, 41× smaller than baseline implementation based on fast test-and-set access L1 memory when constraining 10 percent overhead. When DSP-applications, SCU improves up 92 23 average energy 98 39 average.